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general description the MAX19191 is an ultra-low-power, 8-bit, 10msps analog-to-digital converter (adc). the device features a fully differential wideband track-and-hold (t/h) input. this input has a 440mhz bandwidth and accepts fully differential or single-ended signals. the MAX19191 delivers a typical signal-to-noise and distortion (sinad) of 48.6db at an input frequency of 1.875mhz and a sampling rate of 10msps while consuming only 15.3mw. this adc operates from a 2.7v to 3.6v analog power supply. a separate 1.8v to 3.6v supply powers the digital output driver. in addition to ultra-low operat- ing power, the MAX19191 features three power-down modes to conserve power during idle periods. excellent dynamic performance, ultra-low power, and small size make the MAX19191 ideal for applications in imaging, instrumentation, and digital communications. an internal 1.024v precision bandgap reference sets the full-scale range of the adc to ?.512v. a flexible refer- ence structure allows the MAX19191 to use its internal reference or accept an externally applied reference for applications requiring increased accuracy. the MAX19191 features parallel, cmos-compatible three-state outputs. the digital output format is offset binary. a separate digital power input accepts a voltage from 1.8v to 3.6v for flexible interfacing to different logic levels. the MAX19191 is available in a 5mm 5mm, 28- pin thin qfn package, and is specified for the extended industrial (-40? to +85?) temperature range. for higher sampling frequency applications, refer to the max1195?ax1198 dual 8-bit adcs. for a dual-channel, pin-compatible version, refer to the max19192 data sheet. applications ultrasound and medical imaging battery-powered portable instruments low-power video wlan, mobile dsl, wll receiver digital audio receiver front-end features ultra-low power 15.3mw (normal operation: 10msps) 2 w (shutdown mode) excellent dynamic performance 48.6db snr at f in = 1.875mhz 70dbc sfdr at f in = 1.875mhz 2.7v to 3.6v single analog supply 1.8v to 3.6v ttl/cmos-compatible digital outputs fully differential or single-ended analog inputs internal/external reference option multiplexed cmos-compatible three-state outputs 28-pin thin qfn package evaluation kit available (order MAX19191evkit+) MAX19191 ultra-low-power, 10msps, 8-bit adc ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 MAX19191 5mm x 5mm thin qfn top view in+ exposed pad in- + gnd clk gnd gnd gnd v dd refp refn com refin pd0 pd1 d0 d1 d2 d3 dval d4 d5 d6 d7 ov dd ognd gnd v dd v dd pin configuration ordering information 19-5099; rev 0; 1/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX19191eti+ -40? to +85? 28 thin qfn-ep* MAX19191eti/v+** -40? to +85? 28 thin qfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. ** future product?ontact factory for availability.
MAX19191 ultra-low-power, 10msps, 8-bit adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 10mhz, c refp = c refn = c com = 0.33?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.9v ognd to gnd.......................................................-0.3v to +0.3v in+, in- to gnd ...........-0.3v to the lesser of (v dd + 0.3v or + 3.9v) clk, refin, refp, refn, com to gnd...........-0.3v to the lesser of (v dd + 0.3v or + 3.9v) pd0, pd1 to ognd ...........-0.3v to the lesser of (ov dd + 0.3v or + 3.9v) digital outputs to ognd.............................-0.3v to the lesser of (ov dd + 0.3v or + 3.9v) continuous power dissipation (t a = +70?) 28-pin thin qfn (derated 20.8mw/?above +70?).............................1667mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity inl 0.14 1.00 lsb differential nonlinearity dnl no missing codes over temperature 0.12 1.00 lsb +25c 4 offset error < +25c 6 %fs gain error excludes refp - refn error 2 %fs gain temperature coefficient 30 ppm/c offset (v dd 5%) 0.2 power-supply rejection gain (v dd 5%) 0.05 lsb analog input differential input voltage range v diff differential or single-ended inputs 0.512 v common-mode input voltage range v com v dd /2 v input resistance r in switched capacitor load 540 k input capacitance c in 5 pf conversion rate maximum clock frequency f clk 10 mhz data latency 5.0 clock cycles dynamic characteristics (differential inputs, 4096-point fft) f in = 1.875mhz 47 48.6 signal-to-noise ratio (note 2) snr f in = 3.0mhz 48.6 db f in = 1.875mhz 47 48.6 signal-to-noise and distortion (note 2) sinad f in = 3.0mhz 48.5 db f in = 1.875mhz 59 70.0 spurious-free dynamic range (note 2) sfdr f in = 3.0mhz 70.0 dbc f in = 1.875mhz -71.0 third-harmonic distortion (note 2) hd3 f in = 3.0mhz -71.0 dbc
MAX19191 ultra-low-power, 10msps, 8-bit adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 10mhz, c refp = c refn = c com = 0.33?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units intermodulation distortion imd f in1 = 1.8mhz at -7dbfs, f in2 = 3.0mhz at -7dbfs -64 dbc third-order intermodulation im3 f in1 = 1.8mhz at -7dbfs, f in2 = 3.0mhz at -7dbfs -64 dbc f in = 1.875mhz -69 -57.0 total harmonic distortion (note 2) thd f in = 3.0mhz -67.0 dbc small-signal bandwidth ssbw input at -20dbfs 440 mhz full-power bandwidth fpbw input at -0.5dbfs 440 mhz aperture delay t ad 1.5 ns aperture jitter t aj 2 ps rms overdrive recovery time 1.5 full-scale input 2 ns internal reference (refin = v dd; v refp, v refn , and v com are generated internally) refp output voltage v refp - v com 0.256 v refn output voltage v refn - v com -0.256 v com output voltage v com v dd /2 - 0.15 v dd /2 v dd /2 + 0.15 v differential reference output v ref v refp - v refn 0.512 v differential reference output temperature coefficient v reftc 30 ppm/c maximum refp/refn/com source current i source 2 ma maximum refp/refn/com sink current i sink 2 ma buffered external reference (v refin = 1.024v, v refp , v refn , and v com are generated internally) refin input voltage v refin 1.024 v com output voltage v com v dd /2 - 0.15 v dd /2 v dd /2 + 0.15 v differential reference output v ref v refp - v refn 0.512 v maximum refp/refn/com source current i source 2 ma maximum refp/refn/com sink current i sink 2 ma refin input resistance > 500 k refin input current -0.7 a unbuffered external reference (refin = gnd, v refp , v refn , and v com are applied externally) refp input voltage v refp - v com 0.256 v refn input voltage v refn - v com -0.256 v com input voltage v com v dd /2 v
parameter symbol conditions min typ max units differential reference input voltage v ref v refp - v refn 0.512 v refp input resistance r refp measured between refp and com 4 k refn input resistance r refn measured between refn and com 4 k digital inputs (clk, pd0, pd1) clk 0.7 x v dd input high threshold v ih pd0, pd1 0.7 x ov dd v clk 0.3 x v dd input low threshold v il pd0, pd1 0.3 x ov dd v input hysteresis v hyst 0.1 v clk at gnd or v dd 5 digital input leakage current di in pd0 and pd1 at ognd or ov dd 5 a digital input capacitance dc in 5 pf digital outputs (d7Cd0, a/ b ) output-voltage low v ol i sink = 200a 0.2 x ov dd v output-voltage high v oh i source = 200a 0.8 x ov dd v three-state leakage current i leak 5 a three-state output capacitance c out 5 pf power requirements analog supply voltage v dd 2.7 3.0 3.6 v digital output supply voltage ov dd 1.8 v dd v normal operating mode, f in = 1.875mhz at -0.5dbfs, clk input from gnd to v dd 5.1 5.8 idle mode (three-state), f in = 1.875mhz at -0.5dbfs, clk input from gnd to v dd 5.1 standby mode, clk input from gnd to v dd , pd0 = ognd, pd1 = ov dd 2.9 ma analog supply current i dd shutdown mode, clk = gnd or v dd , pd0 = pd1 = ognd 0.6 5.0 a normal operating mode, f in = 1.875mhz at -0.5dbfs, c l 10pf 1.7 ma idle mode (three-state), dc input, clk = gnd or v dd, pd0 = ov dd , pd1 = ognd 0.1 5.0 standby mode, dc input, clk = gnd or v dd, pd0 = ognd, pd1 = ov dd 0.1 digital output supply current (note 3) i odd shutdown mode, clk = gnd or v dd , pd0 = pd1 = ognd 0.1 5.0 a MAX19191 ultra-low-power, 10msps, 8-bit adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 10mhz, c refp = c refn = c com = 0.33?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
MAX19191 parameter symbol conditions min typ max units timing characteristics clk rise to output data valid t doa 50% of clk to 50% of data, figure 5 (note 4) 1 6 8.5 ns clk rise/fall to dval rise/fall time t d_dval 50% of clk to 50% of dval , figure 5 (note 4) 1 6 8.5 ns pd1 rise to output enable t en pd0 = ov dd 5 ns pd1 fall to output disable t dis pd0 = ov dd 5 ns clk duty cycle 50 % clk duty-cycle variation 10 % wake-up time from shutdown mode t wake, sd (note 5) 20 s wake-up time from standby mode t wake, st (note 5) 5.5 s digital output rise/fall time 20% to 80% 2 ns electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 10mhz, c refp = c refn = c com = 0.33?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) ultra-low-power, 10msps, 8-bit adc _______________________________________________________________________________________ 5 note 1: specifications +25? guaranteed by production test, < +25? guaranteed by design and characterization. note 2: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5dbfs referenced to the amplitude of the digital output. snr and thd are calculated using hd2 through hd6. note 3: the power consumption of the output driver is proportional to the load capacitance (c l ). note 4: guaranteed by design and characterization. not production tested. note 5: sinad settles to within 0.5db of its typical value.
MAX19191 ultra-low-power, 10msps, 8-bit adc 6 _______________________________________________________________________________________ typical operating characteristics (v dd = 3.0v, ov dd = 2.5v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5dbfs, f clk = 10mhz at 50% duty cycle, t a = +25?, unless otherwise noted.) fft plot (differential inputs, 8192-point data record) fft plot (8192 samples) MAX19191 toc01 frequency (mhz) amplitude (dbfs) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 05.0 hd2 hd3 f clk = 10.000000mhz f in = 1.7956543mhz a in = -0.5dbfs fft plot (differential inputs, 8192-point data record) fft plot (8192 samples) MAX19191 toc02 frequency (mhz) amplitude (dbfs) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 0 5.0 hd2 hd3 f clk = 10.000000mhz f in = 2.9870605mhz a in = -0.5dbfs two-tone imd plot (differential inputs, 8192-point data record) MAX19191 toc03 analog input frequency (mhz) amplitude (dbfs) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 0 5.0 f in1 f in2 f clk = 10.000000mhz f in1 = 1.7956543mhz f in2 = 3.001709mhz a in1 = a in2 = -7dbfs fft plot (single-ended inputs, 8192-point data record) fft plot (8192 samples) MAX19191 toc04 frequency (mhz) amplitude (dbfs) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 05.0 hd2 hd3 f clk = 10.000000mhz f in = 1.7956543mhz a in = -0.5dbfs fft plot (single-ended inputs, 8192-point data record) fft plot (8192 samples) MAX19191 toc05 frequency (mhz) amplitude (dbfs) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 0 5.0 hd2 hd3 f clk = 10.000000mhz f in = 2.9870605mhz a in = -0.5dbfs signal-to-noise ratio vs. analog input frequency MAX19191 toc06 f in (mhz) snr (db) 100 80 60 40 20 47 48 49 50 51 52 46 0 120 signal-to-noise and distortion vs. analog input frequency MAX19191 toc07 f in (mhz) sinad (db) 100 80 60 40 20 47 48 49 50 51 52 46 0120 total harmonic distortion vs. analog input frequency MAX19191 toc08 f in (mhz) thd (dbc) 100 80 60 40 20 -75 -70 -65 -60 -80 0120 spurious-free dynamic range vs. analog input frequency MAX19191 toc09 f in (mhz) sfdr (dbc) 100 80 60 40 20 65 70 75 80 60 0 120
MAX19191 ultra-low-power, 10msps, 8-bit adc _______________________________________________________________________________________ 7 signal-to-noise ratio vs. analog input power MAX19191 toc10 analog input power (dbfs) snr (db) -5 -10 -15 -20 -25 20 30 40 50 60 10 -30 0 f in = 2.9902649mhz signal-to-noise and distortion vs. analog input power MAX19191 toc11 sinad (db) 10 20 30 40 50 60 0 analog input power (dbfs) -5 -10 -15 -20 -25 -30 0 f in = 2.9902649mhz total harmonic distortion vs. analog input power MAX19191 toc12 analog input power (dbfs) thd (dbc) -5 -10 -15 -20 -25 -70 -60 -50 -40 -30 -80 -30 0 f in = 2.9902649mhz spurious-free dynamic range vs. analog input power MAX19191 toc13 analog input power (dbfs) sfdr (dbc) -5 -10 -15 -20 -25 40 50 60 70 80 30 -30 0 f in = 2.9902649mhz signal-to-noise ratio vs. sampling rate MAX19191 toc14 f clk (mhz) snr (db) 18 16 14 12 10 8 46 48 50 52 44 620 f in = 2.9902649mhz signal-to-noise and distortion vs. sampling rate MAX19191 toc15 f clk (mhz) sinad (db) 18 16 14 12 10 8 46 48 50 52 44 620 f in = 2.9902649mhz total harmonic distortion vs. sampling rate MAX19191 toc16 thd (dbc) -80 -75 -70 -65 -60 -85 f clk (mhz) 18 16 14 12 10 8 620 f in = 2.9902649mhz spurious-free dynamic range vs. sampling rate MAX19191 toc17 sfdr (dbc) 65 70 75 80 85 60 f clk (mhz) 18 16 14 12 10 8 620 f in = 2.9902649mhz signal-to-noise ratio vs. duty cycle MAX19191 toc18 duty cycle (%) snr (db) 55 50 45 47 48 49 50 46 40 60 f in = 2.9902649mhz typical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.5v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5dbfs, f clk = 10mhz at 50% duty cycle, t a = +25?, unless otherwise noted.)
MAX19191 ultra-low-power, 10msps, 8-bit adc 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.5v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5dbfs, f clk = 10mhz at 50% duty cycle, t a = +25?, unless otherwise noted.) signal-to-noise and distortion vs. duty cycle MAX19191 toc19 duty cycle (%) sinad (db) 55 50 45 47 48 49 50 46 40 60 f in = 2.9902649mhz total harmonic distortion vs. duty cycle thd (dbc) -80 -75 -70 -65 -60 -85 m ax19191 toc20 f in = 2.9902649mhz duty cycle (%) 55 50 45 40 60 spurious-free dynamic range vs. duty cycle sfdr (dbc) 65 70 75 80 85 60 m ax19191 toc21 f in = 2.9902649mhz duty cycle (%) 55 50 45 40 60 integral nonlinearity vs. digital output code MAX19191 toc22 digital output code inl (lsb) 224 192 160 128 96 64 32 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 0256 differential nonlinearity vs. digital output code MAX19191 toc23 digital output code dnl (lsb) 224 192 160 128 96 64 32 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 0256 offset error vs. temperature MAX19191 toc24 temperature ( c) offset error (%fs) 60 35 10 -15 0 0.10 0.20 0.30 0.40 0.50 0.60 -0.10 -40 85 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 gain error (%fs) MAX19191 toc25 gain error vs. temperature temperature ( c) 60 35 10 -15 -40 85 6 -10 1 100 1000 input bandwidth vs. analog input frequency -6 -8 -4 -2 0 2 4 m ax19191 toc26 analog input frequency ( m hz) gain (db) 10 full-power bandwidth -0.5dbfs s m all-signal bandwidth -20dbfs
MAX19191 ultra-low-power, 10msps, 8-bit adc _______________________________________________________________________________________ 9 supply current vs. sampling rate supply current (ma) 2 4 6 8 10 0 m ax19191 toc29 f in = 2.9902649mhz f clk (mhz) 15 10 5 020 a b c a: analog supply current (i vdd ) - internal and buffered external reference modes b: analog supply current (i vdd ) - unbuffered external reference mode c: digital supply current (i ovdd ) - ov dd = 2.5v, all reference modes typical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.5v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5dbfs, f clk = 10mhz at 50% duty cycle, t a = +25?, unless otherwise noted.) reference voltage vs. analog supply voltage MAX19191 toc27 analog supply voltage (v) v refp - v refn (v) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 0.5090 0.5100 0.5110 0.5120 0.5130 0.5080 2.7 3.6 0.5060 0.5080 0.5100 0.5120 0.5140 0.5160 0.5040 v refp - v refn (v) MAX19191 toc28 reference voltage vs. temperature temperature ( c) 60 35 10 -15 -40 85
MAX19191 ultra-low-power, 10msps, 8-bit adc 10 ______________________________________________________________________________________ pin description pin name function 1 in- negative analog input. for single-ended operation, connect in- to com. 2 in+ positive analog input. for single-ended operation, connect signal source to in+. 3, 5, 6, 7, 10 gnd analog ground. connect all gnd pins together. 4 clk converter clock input 8, 9, 28 v dd converter power input. connect to a 2.7v to 3.6v power supply. bypass v dd to gnd with a combination of a 2.2f capacitor in parallel with a 0.1f capacitor. 11 ognd output driver ground 12 ov dd output driver power input. connect to a 1.8v to v dd power supply. bypass ov dd to gnd with a combination of a 2.2f capacitor in parallel with a 0.1f capacitor. 13 d7 three-state digital output. d7 is the most significant bit (msb). 14 d6 three-state digital output 15 d5 three-state digital output 16 d4 three-state digital output 17 dval data valid indicator. this digital output indicates when valid data (dval = 1) is present on the output. 18 d3 three-state digital output 19 d2 three-state digital output 20 d1 three-state digital output 21 d0 three-state digital output. d0 is the least significant bit (lsb). 22 pd1 power-down digital input 1. see table 3. 23 pd0 power-down digital input 0. see table 3. 24 refin reference input. internally pulled up to v dd . 25 com common-mode voltage i/o. bypass com to gnd with a 0.33f capacitor. 26 refn negative reference i/o. conversion range is (v refp - v refn ). bypass refn to gnd with a 0.33f capacitor. 27 refp positive reference i/o. conversion range is (v refp - v refn ). bypass refp to gnd with a 0.33f capacitor. ep exposed pad. internally connected to pin 3. externally connect ep to gnd.
MAX19191 ultra-low-power, 10msps, 8-bit adc ______________________________________________________________________________________ 11 detailed description the MAX19191 uses a seven-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles. at each stage, flash adcs convert the held input volt- ages into a digital code. the following digital-to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. the resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeat- ed until the signal has been processed by all stages. digital error correction compensates for adc compara- tor offsets in each pipeline stage and ensures no miss- ing codes. figure 2 shows the MAX19191 functional diagram. in+ in- t/h digital error correction d0?7 flash adc t/h dac - + x2 1 . 5 bits stage 1 stage 2 stage 7 figure 1. pipeline architecture?tage blocks in+ in- dec / t/h reference system and bias circuits pipeline adc com refin refn refp clk timing ov dd ognd output drivers power control d0?7 / v dd gnd dval pd0 pd1 MAX19191 figure 2. MAX19191 functional diagram
MAX19191 ultra-low-power, 10msps, 8-bit adc 12 ______________________________________________________________________________________ input track-and-hold (t/h) circuits figure 3 displays a simplified functional diagram of the input t/h circuits. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the amplifier input, and open simultaneously with s1, sampling the input wave- form. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differential voltages are held on capacitors c2a and c2b. the amplifiers charge capaci- tors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first stage quantizers and isolate the pipeline from the fast-changing inputs. the wide input bandwidth t/h amplifier allows the MAX19191 to track and sample/hold analog inputs of high frequencies (> nyquist). the adc inputs (in+, in-) can be driven either differentially or sin- gle ended. match the impedance of in+ and in-, and set the common-mode voltage to midsupply (v dd /2) for optimum performance. analog inputs and reference configurations the MAX19191 full-scale analog input range is ? ref with a common-mode input range of v dd /2 ?.2v. v ref is the difference between v refp and v refn . the MAX19191 provides three modes of reference opera- tion. the voltage at refin (v refin ) sets the reference operation mode (table 1). in internal reference mode, connect refin to v dd or leave refin unconnected. v ref is internally generated to be 0.512v ?%. com, refp, and refn are low- impedance outputs with v com = v dd /2, v refp = v dd /2 + v ref /2, and v refn = v dd /2 - v ref /2. bypass refp, refn, and com each with a 0.33? capacitor. in buffered external reference mode, apply a 1.024v ?0% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2 + v refin /4, and v refn = v dd /2 - v refin /4. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. hold hold clk internal nonoverlapping clock signals track track s3b s3a com s5b s5a in+ in- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b MAX19191 figure 3. internal t/h circuits
MAX19191 ultra-low-power, 10msps, 8-bit adc ______________________________________________________________________________________ 13 in unbuffered external reference mode, connect refin to gnd. this deactivates the on-chip reference buffers for com, refp, and refn. with their buffers shut down, these nodes become high-impedance inputs (figure 4) and can be driven through separate, external reference sources. drive v com to v dd /2 ?0%, drive v refp to (v dd /2 +0.256v) ?0%, and drive v refn to (v dd /2 - 0.256v) ?0%. bypass refp, refn, and com each with a 0.33? capacitor. for detailed circuit suggestions and how to drive this dual adc in buffered/unbuffered external reference mode, see the applications information section. clock input (clk) clk accepts a cmos-compatible signal level. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the exter- nal clock, use a clock with low jitter and fast rise and fall times (< 2ns). in particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr performance of the on-chip adcs as follows: where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the MAX19191 clock input operates with a v dd /2 voltage threshold and accepts a 50% ?0% duty cycle (see the typical operating characteristics ). system timing requirements figure 5 shows the relationship between the clock, ana- log inputs, dval indicator, and the resulting output data. input data is sampled on the rising edge of the clock signal (clk). five clock cycles later, output data is updated on the rising edge of the clk. the dval indicator follows clk with a typical delay time of 6ns and remains high when the output data is valid. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles. output data remains valid for half a clock period. snr ft in aj log = ? ? ? ? ? ? 20 1 2 figure 4. unbuffered external reference mode impedance v refin reference mode > 0.8 x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33f capacitor. 1.024v 10% buffered external reference mode. an external 1.024v 10% reference voltage is applied to refin. v ref is internally generated to be v refin /2. bypass refp, refn, and com each with a 0.33f capacitor. bypass refin to gnd with a 0.1f capacitor. < 0.3v unbuffered external reference mode. refp, refn, and com are driven by external reference sources. v ref is the difference between the externally applied v refp and v refn . bypass refp, refn, and com each with a 0.33f capacitor. table 1. reference modes MAX19191 1 . 5v 1 . 25v 1 . 75v 62 . 5 a 0 a com refn refp 4k ? 4k ? 62 . 5 a
MAX19191 ultra-low-power, 10msps, 8-bit adc 14 ______________________________________________________________________________________ digital output data (d0?7), data valid indicator (dval) d0?7 and dval are ttl/cmos-logic compatible. the digital output coding is offset binary (table 2, figure 6). the capacitive load on the digital outputs d0?7 should be kept as low as possible (< 15pf) to avoid large digital currents feeding back into the analog por- tion of the MAX19191 and degrading its dynamic per- formance. buffers on the digital outputs isolate them from heavy capacitive loads. to improve the dynamic performance of the MAX19191, add 100 ? resistors in series with the digital outputs close to the MAX19191. refer to the MAX19191 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 100 ? series resistors. power modes (pd0, pd1) the MAX19191 has four power modes that are con- trolled with pd0 and pd1. four power modes allow the MAX19191 to efficiently use power by transitioning to a low-power state when conversions are not required (table 3). shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the MAX19191 and placing the outputs in three-state. the wake-up time from shutdown mode is dominated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 20?. when operating in the unbuffered external refer- ence mode, the wake-up time is dependent on the external reference drivers. when the outputs transition from three-state to on, the last converted word is placed on the digital outputs. in standby mode, the reference and clock distribution circuits are powered up, but the pipeline adc is unpowered and the outputs are in three-state. the wake-up time from standby mode is dominated by the t cl t ch t clk t do t d_dval t d_dval 5 clock-cycle latency dval d0?7 valid d1 xx valid d2 xx valid d3 xx valid d4 xx valid d5 xx xx valid d6 in clk figure 5. system timing diagram figure 6. transfer function input voltage (lsb) -1 -126 -125 256 2 x v ref 1lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+1 -127 +126 +128 +127 -128 +125 (com) (com) offset binary output code (lsb) 0000 0000 0000 0001 0000 0010 0000 0011 1111 1111 1111 1110 1111 1101 0111 1111 1000 0000 1000 0001
MAX19191 ultra-low-power, 10msps, 8-bit adc ______________________________________________________________________________________ 15 5.5? required to activate the pipeline adc. when the outputs transition from three-state to on, the last con- verted word is placed on the digital outputs. in idle mode, the pipeline adc, reference, and clock distribution circuits are powered, but the outputs are forced to three-state. the wake-up time from idle mode is dominated by the 5ns required for the output drivers to start from three-state. when the outputs transition from three-state to on, the last converted word is placed on the digital outputs. in the normal operating mode, all sections of the MAX19191 are powered. applications information the circuit of figure 7 operates from a single 3v supply and accommodates a wide 0.5v to 1.5v input common- mode voltage range for the analog interface between differential, dc-coupled signal source and a high-speed adc. r iso isolates the op amp output from the adc capacitive input to prevent ringing and oscilla- tion. c in filters high-frequency noise. using transformer coupling an rf transformer ( figure 8) provides an excellent solu- tion to convert a single-ended source signal to a fully dif- ferential signal, required by the MAX19191 for optimum performance. connecting the center tap of the trans- former to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive require- ments. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. in general, the MAX19191 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for high input frequencies. in differential input mode, even-order harmonics are lower as both inputs are balanced, and the adc input only requires half the signal swing compared to single- ended mode. differential input voltage (in+ - in-) differential input (lsb) offset binary (d7Cd0) output decimal code +127 (+ full scale - 1 lsb) 1111 1111 255 +126 (+ full scale - 2 lsb) 1111 1110 254 +1 1000 0001 129 0 (bipolar zero) 1000 0000 128 -1 0111 1111 127 -127 (- full scale + 1 lsb) 0000 0001 1 -128 (- full scale) 0000 0000 0 v ref 127 128 v ref 126 128 v ref 1 128 v ref 0 128 -v ref 1 128 -v ref 127 128 -v ref 128 128 table 2. output codes vs. input voltage pd0 pd1 power mode adc internal reference clock distribution outputs 0 0 shutdown off off off three-state 0 1 standby off on on three-state 1 0 idle on on on three-state 1 1 normal operating on on on on table 3. power logic
MAX19191 ultra-low-power, 10msps, 8-bit adc 16 ______________________________________________________________________________________ single-ended ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica- tion. amplifiers such as the max4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. buffered external reference drives multiple adcs the buffered external reference mode allows for more control over the MAX19191 reference voltage and allows multiple converters to use a common reference. to drive one MAX19191 in buffered external reference mode, the external circuit must sink 0.7?, allowing one reference circuit to easily drive the refin of multiple converters to 1.024v ?0%. figure 10 shows the max6061 precision bandgap ref- erence used as a common reference for multiple con- verters. the 1.248v output of the max6061 is divided down to 1.023v as it passes through a one-pole, 10hz, lowpass filter to the max4250. the max4250 buffers the 1.023v reference before its output is applied to the MAX19191. the max4250 provides a low offset voltage (for high gain accuracy) and a low noise level. MAX19191 in- com in+ a v = 6v/v v com = v dd /2 v com = 0 . 5v to 1 . 5v v sig = 85mv p-p r iso 22 ? r iso 22 ? r11 600 ? r9 600 ? r2 300 ? operational amplifiers choose either of the max4452/max4453/max4454 single/ dual/quad 3v, 200mhz op amps for use with this circuit . connect the positive supply rail (v cc ) to 3v . connect the negative supply rail (v ee ) to ground . decouple v cc with a 0 . 1 f capacitor to ground . resistor networks resistor networks ensure proper thermal and tolerance matching . for r1, r2, and r3 use a network such as vishay's 3r model number 300192 . for r4?11, use a network such as vishay's 4r model number 300197 . r10 600 ? r8 600 ? r5 600 ? r4 600 ? r7 600 ? r6 600 ? c in 5pf c in 5pf r1 600 ? r3 600 ? figure 7. dc-coupled differential input driver
MAX19191 ultra-low-power, 10msps, 8-bit adc ______________________________________________________________________________________ 17 MAX19191 t1 n . c . v in 6 1 5 2 4 3 22pf 22pf 0 . 1 f 0 . 1 f 2 . 2 f 25 ? 25 ? minicircuits tt1-6-kk81 in- in+ com figure 8. transformer-coupled input drive com in+ in- 0 . 1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0 . 1 f r iso 50 ? r iso 50 ? refp refn v in max4108 MAX19191 figure 9. using an op amp for single-ended, ac-coupled input drive max4250 3v 2 4 2 1 . 248v 3 5 10hz lowpass filter 1 15 ? 1 refin v dd MAX19191 n = 1 24 gnd 1 . 023v note: one front-end reference circuit provides 15ma of output drive and supports over 1000 MAX19191s . 3 0 . 1 f 0 . 1 f 3v 1 f 1% 20k ? 1% 90 . 9k ? 0 . 1 f 2 . 2 f 0 . 1 f refp 27 0 . 33 f refn 26 0 . 33 f com 25 0 . 33 f refin v dd MAX19191 n = 1000 24 gnd 0 . 1 f refp 27 0 . 33 f refn 26 0 . 33 f com 25 0 . 33 f max6061 figure 10. external buffered (max4250) reference drive using a max6061 bandgap reference
MAX19191 ultra-low-power, 10msps, 8-bit adc 18 ______________________________________________________________________________________ unbuffered external reference drives multiple adcs the unbuffered external reference mode allows for pre- cise control over the MAX19191 reference and allows multiple converters to use a common reference. connecting refin to gnd disables the internal refer- ence, allowing refp, refn, and com to be driven directly by a set of external reference sources. figure 11 shows the max6066 precision bandgap ref- erence used as a common reference for multiple con- verters. the 2.500v output of the max6066 is followed by a 10hz lowpass filter and precision voltage-divider. the max4254 buffers the taps of this divider to provide the 1.75v, 1.5v, and 1.25v sources to drive refp, refn, and com. the max4254 provides a low offset voltage and low noise level. the individual voltage fol- lowers are connected to 10hz lowpass filters, which fil- ter both the reference-voltage and amplifier noise to a level of 3nv/ hz . the 1.75v and 1.25v reference volt- ages set the differential full-scale range of the associat- ed adcs at ?.5v. the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. with the outputs of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters sup- port as many as 160 MAX19191s. max4254 1/4 47 ? 3v 2 2 2 . 500v 3 1 1 refp v dd MAX19191 n = 1 27 gnd note: one front-end reference circuit supports up to 160 MAX19191s . 3 0 . 1 f 10 f 6v 1 f 1% 30 . 1k ? 1% 10 . 0k ? 0 . 1 f 2 . 2 f 330 f 6v 0 . 33 f 26 24 0 . 33 f refn refin refin 25 0 . 33 f com max6066 1 . 748v 1% 10 . 0k ? 1% 49 . 9k ? refp v dd MAX19191 n = 160 27 gnd 0 . 33 f 26 24 0 . 33 f refn 25 0 . 33 f com 1 . 47k ? max4254 47 ? 6 5 7 10 f 6v 330 f 6v 1 . 498v 1 . 47k ? 47 ? 9 10 8 10 f 6v 330 f 6v 1 . 248v max4254 1 . 47k ? 1m ? max4254 13 12 14 11 4 0 . 1 f uncommitted 1m ? 3v 1/4 1/4 1/4 figure 11. external unbuffered reference driving 160 adcs with the max4254 and max6066
MAX19191 ultra-low-power, 10msps, 8-bit adc ______________________________________________________________________________________ 19 grounding, bypassing, and board layout the MAX19191 requires high-speed board layout design techniques. refer to the MAX19191 evaluation kit data sheet for a board layout reference. locate all bypass capacitors as close as possible to the device, preferably on the same side as the adc, using surface- mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? bipolar capacitor. bypass ov dd to ognd with a 0.1? ceramic capacitor in parallel with a 2.2? bipolar capacitor. bypass refp, refn, and com each to gnd with a 0.33? ceramic capacitor. multilayer boards with separated ground and power planes produce the highest level of signal integrity. use a split ground plane arranged to match the physical location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc? package. connect the MAX19191 exposed backside pad to gnd. join the two ground planes at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. the ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital sys- tems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from the sensitive analog traces of either channel. make sure to isolate the analog input lines to each respective con- verter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the MAX19191 are measured using the end-point method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. offset error ideally, the midscale MAX19191 transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. gain error ideally, the full-scale MAX19191 transition occurs at 1.5 lsb below full-scale. the gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. dynamic parameter definitions aperture jitter figure 12 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken ( figure 12). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 n + 1.76 hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 12. t/h aperture timing
MAX19191 ultra-low-power, 10msps, 8-bit adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 ? 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. the intermodulation prod- ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2 f1). the individual input tone levels are at -7dbfs. third-order intermodulation (im3) im3 is the power of the worst third-order intermodula- tion product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. the third-order intermodulation products are (2 x f1 f2), (2 x f2 f1). the individual input tone levels are at -7dbfs. power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supplies are moved ?%. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. note that the track/hold (t/h) performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. chip information process: cmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. thd vvvvv v log = ++++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 1 enob sinad . . = -176 602 package type package code document no. 28 tqfn-ep t2855+8 21-0140

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